(1) Field of the Invention
The invention relates to an integrated circuit memory cell structure and array architecture, and, more particularly, to a novel EEPROM cell structure and array architecture with improved scalability, manufacturability, and endurance.
(2) Description of the Prior Art
The electrically erasable, programmable read only memory (EEPROM) is widely used in today's electronic devices. This is especially true for hand held devices. Because of the advantages of nonvolatility, low operating current, and unique byte alterability, the EEPROM has become an important component in the memory market.
Flash memory devices have been developed more recently than EEPROM devices. Both memory types are nonvolatile. However, the Flash memory lacks the same byte erasing and re-programming options of the EEPROM. Generally, the data of the Flash memory must be altered in large sized blocks. This limitation makes Flash memory less desirable for many applications.
The basic EEPROM is a double polysilicon gate transistor. The data is stored on the floating gate as an electron charge. This electron charge can be altered to thereby change the threshold voltage of the transistor as controlled by the control gate. During a reading operation, the threshold voltage of the cell will determine the current flowing through the channel region of the memory cell. This current level can then be sensed and decoded into a logical ‘0’ or ‘1.’ To change the stored data, two operations may be performed on the EEPROM cell to increase or decrease the charge stored on the floating gate: erase and program. For a conventional EEPROM cell, both erase and program operations are based on the well-known Fowler-Nordheim (FN) tunneling mechanism.
As the manufacturing technology of semiconductors is scaled down to smaller device geometry, thinner dielectric layers, and narrower channel widths, the EEPROM technology has experienced many problems. Most of these problems are because the conventional EEPROM cell requires a high voltage of between about 12 Volts and 15 Volts in the bit line diffusion to perform the erase and program operations. In addition, the conventional EEPROM cell structure is very complex. These two factors create manufacturing and scaling difficulties. As a result, the manufacturing cost of the conventional EEPROM has become higher, the cell size has become bigger and un-shrinkable, and the array density is limited to low density devices. The present invention is designed to solve these problems of the prior art by providing a simpler EEPROM cell structure with better scalability and longer endurance cycles.
Referring now to FIG. 1, a prior art, conventional EEPROM cell is shown. The cell includes two transistors, a floating gate transistor 101 and a selection transistor 100 formed on a substrate 112. The floating gate transistor 101 is the memory cell device to store the data. The selection transistor 100 performs an isolation function to prevent the data stored on the floating gate transistor 101 from being disturbed by a high voltage applied to the bit line 106. The erasing, programming, and reading conditions for the EEPROM cell are summarized below in Table 1.
TABLE 1Operation Conditions for Conventional EEPROM Cell.OperationVdVsgVcgVsEraseSelected0 V0 V+10 V0 VDeselected0 V0 V0 V0 VProgramSelected+10 V>= +100 V0 VDeselected0 VV0 V0 V>= +10VReadSelectedι + 1 VVddVdd0 VDeselected0 V0 VVdd0 V
For an erase operation, the control gate 104 of the selected cell is applied with a positive high voltage of, for example, about +12 Volts. The drain diffusion region 109 of the cell is applied with a relatively low voltage of about 0 Volts. Under such bias conditions, the large voltage difference between the control gate 104 and the diffusion region 109 will create a strong electric field across the tunnel oxide window 103 located between the floating gate 105 and diffusion region 109. This strong electric field will overcome the tunneling energy barrier of the tunnel oxide and cause the FN tunneling phenomenon to occur. The electron charge will be induced and injected from the diffusion region 109 to the floating gate 105 through the tunnel oxide window 103. This injection causes the threshold voltage of the floating gate transistor 101 to increase and makes the cell a logical data ‘1’ cell.
The programming operation is performed in the opposite way. For the cell being programmed, the drain diffusion 109 is biased to a large positive voltage, such as about +12 Volts. The control gate 104 is bias to the low voltage of about 0 Volts. This condition will cause the same strong electric field but in the reverse direction. The electron charge is injected from the floating gate 105 to the drain diffusion 109 through the tunnel oxide window 103. The programmed cell threshold voltage is decreased, and it becomes a data ‘0’ cell.
Note that for the prior art EEPROM cell, both the erase and the program operations use the tunnel oxide window 103 to transfer the electron charge. In addition, this electron charge is transferred to and from the floating gate 105 and the drain diffusion 109. However, this prior art EEPROM has several serious drawbacks.
First, the prior art cell requires an extremely high voltage be applied to the bit line 106 as well as to the drain diffusion 109 during erase and program operations. This high voltage requirement limits the scalability of the memory cells. The large drain voltage requires a deep diffusion junction to provide adequate reverse bias breakdown voltage between the junction and the substrate. In addition, large spaces must be provided between the diffusion regions and the adjacent bit lines to prevent the high voltage from causing a field oxide punch through. Finally, the channel length of the selection transistor must be kept large to prevent a channel punch through. As a result, the conventional EEPROM device cannot be readily scaled down. As a further result, today's EEPROM technology is far behind the most advanced Flash memory technology that typically requires lower erase and program voltages. Because of the necessarily large cell size of the EEPROM, most EEPROM-based products are limited to the low density market such as the 512 Kb memory.
Second, the conventional EEPROM memory cell requires complex processing steps to manufacture. At least three different n-type ion implantations must be used to generate the required diffusions for the N− tunneling window 109, the lightly doped source 110, and the heavily doped drain and source regions 107, 108, and 111. Further, at least two additional deposition and etching sequences must be added to the process flow to create the tunnel oxide window 103 and the thicker gate oxide layer 113 under the floating gate 105. Compared with a conventional Flash memory cell, the conventional EEPROM memory cell is more difficult and expensive to manufacture and has a lower yield.
Third, the complex topology of the conventional EEPROM cell also creates many problems and difficulties in aligning the process steps. Particularly, the tunnel oxide window 103 and the drain diffusion 109 create problems. Since the drain diffusion 109 must sustain a high voltage, it is very important that the entire tunnel oxide window 103 be located inside the region defined by the underlying drain diffusion 109. This will result in optimum diffusion to substrate breakdown voltage. However, if a mask misalignment occurs, the tunnel oxide window 103 may extend beyond the diffusion region 109 and cause the edge of the drain diffusion 109 to be exposed under the tunnel oxide window 103. This occurrence will result in a lowered diffusion 109 to substrate 112 breakdown voltage. Under certain operating conditions, the high voltage supplies of the device may not be able to sustain the resulting leakage current and the erase and program operations may fail. In addition, the diffusion region must extend under the field oxide region (not shown) between adjacent bit lines to avoid exposing the diffusion edge under the tunnel oxide window in the edge of the field oxide. Therefore, the diffusion region has to be extended about 0.5 microns beyond the field oxide edge according to a 2 microns process described in the prior art.
From the above description of the conventional EEPROM cell, many disadvantages have been described. The large erasing and programming voltages and the complex cell structure create problems and difficulties for scaling down the technology. As a result a novel EEPROM cell and array structure has been achieved to reduce the operational voltages, reduce the cell complexity, and to improve the scalability.